1. Field of the Invention
The present invention relates to large register files and methods for operation of the same.
2. Art Background
Modern processors typically include extensive execution resources to support concurrent processing of multiple instructions. These execution resources receive data from a hierarchy of storage structures with varying access latencies. One or more register files are located on the processor chip to provide data to the execution resources with very low latencies. Other storage structures include on-chip caches, off-chip caches, and a main memory, which provide data to execution resources with correspondingly longer latencies. Because register files are a primary source of data for execution resources, high performance processors typically employ larger register files, which have more off register cells. These larger register files maintain more data near the processor""s execution resources, where it can be accessed with relatively low latency by multiple execution units.
However, as the size of the register files increase and lower on-off current ratios are utilized, as are foreseen in deep sub-micron MOSFETs, the detrimental effects of steeply increasing sub-threshold currents on the robustness of large register files must be addressed.
The problem is illustrated by reference to FIG. 1. In this illustration, sixteen register file (RF) cell read ports 15 are connected to a local bitline 20 that is precharged by the signal CLK 25. In a worst-case scenario where the data value stored in the 16 cells is a logic 1, considerable charge leakage occurs through the Mread transistors 30. To counteract this, the size-of the keeper transistor Mkeep 35 must be increased, which degrades performance.